EDN

Intilop’s 16K Concurrent TCP & UDP Session Hardware Accelerator Core (TOE & UOE) Now Available for Immediate Data Center Deployment

MILPITAS, Calif., Oct. 22, 2014 /PRNewswire/ — Intilop, Inc. a pioneer, most respected and recognized leader in providing Ultra-Low latency and Hyper Performance Complex Networking Protocol ...
Design-Reuse

Intilop releases a Full TCP & UDP Host-Side Application interface for Altera and Xilinx FPGAs for Software's use that is implemented in Low latency hardware

Milpitas, CA., October 12, 2015-- Intilop, Inc., a pioneer, most respected and recognized leader in providing Ultra-Low latency and Hyper Performance Complex Networking Protocol Accelerators like Full ...
Business Wire

PLDA Introduces QuickTCP - Full Hardware 10G TCP/IP Stack IP core for FPGA

SAN JOSE, Calif.--(BUSINESS WIRE)--PLDA, the industry leader in interconnect IP, today unveiled its 10Gb TCP/IP Hardware stack IP core. PLDA’s QuickTCP IP solution is a 100% RTL designed IP, compliant ...
Design-Reuse

Intilop releases their 7 Gen. 1024 Full TCP & UDP Session Hardware Accelerator that requires no external memory on Altera & Xilinx FPGAs for all Hyper Performance Networking ...

This 7th generation TCP & UDP Accelerator is an optimized version of their 16K Session Core uses internal FPGA memory only, exhibits receive latency of 77 nanoseconds with 97% TCP throughput, ...
EDN

Intilop releases their 7 Gen. 1024 Full TCP & UDP Session Hardware Accelerator that requires no external memory on Altera & Xilinx FPGAs for all Hyper Performance Networking ...

This deployment-ready, pre-verified solution provides networking OEMs an Ultra-low-latency and Hyper-performance for all networking equipment segments that have to process TCP Protocol. Available in ...