XJTAG announced the release of a free software for PADS® Schematic Design that will significantly increase the Design for Test and Debug capabilities of the schematic capture and PCB design ...

At times physical design engineers find it difficult to relate with the additional timing modes introduced in PnR due to DFT insertion. These additional timing modes and related issues could be ...

With advanced technology nodes, the SoCs are growing in density and gate count. This creates challenges regarding the testability, and more importantly, the test cost. The design complexity and size ...

As design size and complexity increase, so too does the cost of test. Both the design community and the test industry are looking at various approaches to lower the cost of manufacturing test. This ...

When existing advanced 2D designs already push the limits of design-for-test (DFT) tools, what hope do developers have of managing DFT for 3D devices? Can anyone afford the tool run time, on-chip area ...

Westford, MA; Munich, Germany; and Cambridge, UK. Zuken and XJTAG have released a plugin that will enhance Zuken’s CR-8000 with a design-for-test (DFT) capability, improving test coverage by allowing ...