EDN

Tool duo touts process-aware DFM

Santa Cruz, Calif. — Pursuing a new breed of design-for-manufacturability (DFM) tools for 45-nanometer ICs, Synopsys Inc. this week will announce Seismos and Paramos, two “process-aware” tools that ...
Semiconductor Engineering

Tuning Design And Process For High-NA EUV Stitching

Upcoming 14A and 10A process nodes will use high-NA EUV anamorphic scanners, which will require two stitched half-fields to achieve the equivalent wafer exposure area of previous-generation scanners, ...
EDN

Synopsys Tackles 45nm Process-Related Variation

Revealing another piece of its DFM tool arsenal, Synopsys Inc. today detailed its new process-aware design-for-manufacturing (PA-DFM) tools, meant to analyze variability effects at the custom/analog ...
Electronic Design

Transitioning To Manufacturing-Aware Design

At each transition to more advanced design and manufacturing technologies, the physical design process has undergone a transformation in breadth of requirements and depth of capability... At each ...
Design-Reuse

Synopsys' Custom Compiler Certified for TSMC 10-nm and 7-nm FinFET Process Nodes

MOUNTAIN VIEW, Calif., Mar. 30, 2016 – Synopsys, Inc. (Nasdaq: SNPS) today announced that the company's new Custom Compiler™ tool (see today's news release) has been certified by TSMC for 10-nanometer ...
Semiconductor Engineering

Moving Beyond Geometries: Context-Aware Verification Improves Design Quality And Reliability

Context-aware checks integrate physical and electrical information to evaluate a wide range of design conditions, from advanced design rule compliance, to circuit and reliability verification, to ...